1. Technical Field
The present invention relates to semiconductor memory apparatuses, and more particularly, to a semiconductor memory apparatus including a write driver.
2. Related Art
In general, a semiconductor memory apparatus repeats a read/write operation. The read operation is an operation that outputs data stored in a selected memory cell to the outside of the semiconductor memory apparatus, and the write operation is an operation that stores data input from the outside of the semiconductor memory apparatus in to the selected memory cell.
Since a data input/output speed of the semiconductor memory apparatus is an important element that determines an operation speed of a system to which the semiconductor memory apparatus is applied, a technology for improving the operation speed of the semiconductor memory apparatus has been researched.
In order to improve the operation speed of the semiconductor memory apparatus, a synchronous DRAM (SDRAM) that controls internal circuits in synchronization with a clock signal generated from the outside of the synchronous DRAM has been developed.
The synchronous DRAM may be classified into a single data rate SDRAM (hereinafter, referred to as SDR SDRAM) and a double data rate SDRAM (hereinafter, DDR SDRAM). In the SDR SDRAM, one data is input or output during one cycle of an external clock signal in response to a rising edge or a falling edge of the external clock signal. Meanwhile, in the DDR SDRAM, two data are input or output during one cycle of an external clock signal in response to both a rising edge and a falling edge of the external clock signal. Thus, a bandwidth of the DDR SDRAM may be at a maximum two times wider than a bandwidth of the SDR SDRAM.
As shown in FIG. 1, in a general DDR2 SDRAM, a column active signal CACTV and a data input pulse DINCLKP are generated after two clock cycles which start when inputting a clock signal CLK including a write command WT. Data is loaded to a GIO (global input/output) line in synchronization with a rising edge of the data input pulse DINCLKP.
The write driver receives the data that is stored in the GIO line in response to the column active signal CACTV. At this time, a predetermined amount of delay time is required to receive the data loaded to the GIO line, and the delay time is ensured by a general delay member, for example, a circuit member that includes a plurality of inverters and RC elements. That is, the write driver is supplied with a bank write enable signal BWEN that adjusts the amount of time needed to receive the data loaded to the GIO line by the delay member. Specifically, when the bank write enable signal BWEN is at a high level, the write driver receives the data from the GIO line, and when the bank write enable signal BWEN is at a low level, the write driver stores the data loaded to the GIO line in a latch circuit that is included in the write driver.
Thus, in order to securely recognize the data from the GIO line, it is preferable to allow a high pulse interval of the bank write enable signal BWEN to be located at the center of a pulsing interval (H or L) of the signal from the GIO line. In the related art, the number of components that constitute a delay member is adjusted such that a pulsing interval of the bank write enable signal BWEN is located at the center of the high or low pulsing interval of the signal from the GIO line.
However, in the case of a DDR2 SDRAM that has a memory capacity of 1G byte, the length of the GIO line is about 15000 μm because the DDR2 SDRAM has an 8-bank structure. When the length of the GIO line is increased, a resistance value of the GIO line is increased. Therefore, a parasitic RC delay time is generated, which decreases a data transmission rate. For this reason, the bank write enable signal BWEN is delayed for a predetermined time longer than a set delay time. As a result, since the bank write enable signal BWEN is not generated at a proper timing, an error may occur when the write driver receives the data.
Further, the general delay member is composed of a delay circuit that includes a plurality of inverters, a resistor, and a capacitor, and transistors constituting the inverters, the resistor, and the capacitor may be affected by a voltage, a temperature, and a frequency. That is, in the delay member that includes the transistors, the resistor, and the capacitor that are normally affected by the outside environment, when the power and voltage are increased, a delay time is decreased, and when the power and voltage are decreased, the delay time is increased.
Therefore, in the bank write enable signal BWEN whose pulse generating interval is determined by the delay member, the pulse generating interval may be changed due to the length of the GIO line, process variables, or the like. In the case of a low-voltage and high-frequency element such as the DDR2 SDRAM, the high pulse interval of the bank write enable signal BWEN may be generated outside the high pulse interval of the signal from the GIO line.
For this reason, it is difficult for the write driver according to the related art to securely receive the data loaded to the GIO line.